Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others.
Flash memory devices can be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Uses for flash memory include memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among other electronic devices.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line, which is commonly referred to in the art as a “word line”. However each memory cell is not directly coupled to a data line (which is commonly referred to as a bit line, in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a data line, where the memory cells commonly coupled to a particular data line are referred to as a “column”.
Memory cells in a NAND array architecture can be programmed to a targeted, e.g., desired, program state. For example, electric charge can be placed on or removed from a charge storage structure, e.g., a floating gate or charge trap, of a memory cell to put the cell into one of a number of program states. For example, a single level cell (SLC) can be programmed to one of two program states, such as to represent a binary data value, e.g., “1” or “0”, stored by the cell. In a NAND architecture, a memory cell is erased prior to being programmed, and the cell is not reprogrammed prior to being erased. The memory cells of a NAND array are erased together in groups referred to as “blocks”. Each block can include a number of pages of memory cells that are programmed and/or read together as a group. As such, pages of memory cells of a particular block are not reprogrammed individually without first erasing the entire block. Requiring a block to be erased before cells of the block can be reprogrammed can increase the wear of a memory device, among other drawbacks.